首页> 外文期刊>Journal of Technical Physics >SIMPLE MODELING APPROACH FOR LINE IMPEDANCE OF ON-CHIP CMOS INTERCONNECTS
【24h】

SIMPLE MODELING APPROACH FOR LINE IMPEDANCE OF ON-CHIP CMOS INTERCONNECTS

机译:片上CMOS互连线阻抗的简单建模方法

获取原文
获取原文并翻译 | 示例
           

摘要

Simple and accurate closed-form model enabling to calculate frequency-dependent distributed inductance and associated distributed series resistance per-unit-length of single on-chip interconnects on a lossy silicon substrate is presented. The closed-form formulas for the frequency-dependent series impedance parameters are obtained using a closed-form integration method and the vector magnetic potential equation. The proposed frequency-dependent inductance L(ω) and resistance R(ω) per-unit-length formulas are shown to be in good agreement with the electromagnetic solutions.
机译:提出了一种简单而精确的闭合形式模型,该模型能够计算有损耗硅基板上单个芯片上互连的每单位长度的频率相关分布电感和相关的分布串联电阻。使用封闭形式的积分方法和矢量磁势方程,可以得出频率相关的串联阻抗参数的封闭形式的公式。所提出的频率相关的电感L(ω)和电阻R(ω)的每单位长度公式与电磁解决方案非常吻合。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号