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Design of all-optical parallel multipliers using semiconductor optical amplifier-based Mach-Zehnder interferometers

机译:使用基于半导体光放大器的Mach-Zehnder干涉仪的全光并行乘法器设计

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Due to the benefits of low power, high bandwidth and complementary metal-oxide-semiconductor (CMOS) compatibility, the design of optical circuits has spurred great attention among researchers in the domain of electronic design automation. With this motivation, all-optical combinational and sequential circuits such as adders, multiplexers, multipliers and flip-flops have been explored in recent times. In this paper, we have explored the designs of all-optical array multiplier and four types of parallel multipliers (carry save adder multiplier, Wallace tree multiplier, Dadda multiplier and reduced area multiplier) using two different design approaches named as Design1 and Design2. In order to design these multipliers, semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometers (MZIs) have been used as the basic optical component. The basic MZI switch, full adder and 2-bit multiplier have been simulated using OptiSystem software to analyze the power loss. Furthermore, an all-optical merged multiplier has been designed, which is often used in digital signal processors. In comparison with other designed multipliers, it is evident from the simulation results that the MZI-based reduced area multiplier of Design1 approach has the highest performance in terms of speed, while the MZI-based carry save adder (CSA) multiplier with Design1 approach has the least optical cost.
机译:由于低功率,高带宽和互补金属 - 氧化物半导体(CMOS)兼容性的益处,光电电路的设计在电子设计自动化领域的研究人员中造成了很大的关注。利用这种动机,最近探讨了所有光学组合和顺序电路,例如加法器,多路复用器,乘法器和触发器。在本文中,我们探讨了所有光学阵列乘数和四种类型的并联乘法器的设计(使用Save Adder乘数,Wallace树乘数,Dadda乘数和缩小区域乘数)使用两种不同的设计方法,并设计为Design1和Design2。为了设计这些乘法器,已使用半导体光学放大器(SOA)被基下的Mach-Zehnder干涉仪(MZIS)作为基本光学组件。使用OptiSystem软件模拟基本MZI开关,全加法器和2位乘数来分析功率损耗。此外,设计了全光合并乘法器,该乘法器通常用于数字信号处理器。与其他设计的乘法器相比,从模拟结果明显看出,设计1方法的MZI基础的降低区域乘数在速度方面具有最高性能,而基于MZI的随身保存加法器(CSA)乘法器具有设计1方法最小的光学成本。

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