New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2~m) Under Polynomial Basis and Normal Basis Representations

摘要

A new bit-parallel systolic multiplier over GF (2~m) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m~2 identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2~m). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.