A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000

摘要

The Arithmetic encoder (AE) is a throughput bottleneck of the entire JPEG2000 encoding system. But its sequential nature leads to a difficulty to improve its throughput. To overcome this bottleneck, a high-throughput AE capable of encoding one symbol per clock is proposed. First, the correlations between the sequential pairs of context and its decision are analyzed. Moreover, the burst number of CX and the burst number of the index value are studied. Due to these analyses, a conclusion is drawn in order to prevent the AE from stalling when the burst number of the context is larger than one. Based on this conclusion, an "index-arbiter" method is introduced, which increased the throughput greatly. Furthermore, the probabilities of different adjusting manners for the interval register A and code register C before renormalization are given. On the basis of these data, a detector of leading-zero is proposed to simplify the renormalization procedure. Finally, the total number and the max burst number of the two-byte emission are given. According to these results, a FIFO size of 43*4 is introduced to prevent the pipeline from pause when two-byte emission occurs. The proposed architecture is synthesized with TSMC0.18 mu m HS technology library of ARM Company. The implementation result shows that the throughput of the proposed architecture is 547Msymbols/s with an area of 79,012.84 mu m(2). Compared with the paper Rhu and Park (IEEE Transactions on Circuits and Systems for Video Technology, 20(3),446-451, 2010), the throughput has been increased by 37 %.