JPEG2000算术编码器的算法优化和VLSI设计

摘要

The algorithm and the hardware implementation of Arithmetic Coder (AC) in JPEG2000 are studied. A new kind of the sequence structure of the Renormalization Procedure (RP) is proposed. With the independent total-shift prediction procedure added,the current context can be processed serially by AC without loop computation.Based on the proposed algorithm, the 3-stage pipeline architecture with a slave pipeline is designed, where the pipeline is used to process the common situation of no byte-output and the slave pipeline is used to detect and process the byte-output situation separately, in order to reduce the critical path of the sub circuits.The synthesis result by the technology library of TSMC 0.18μm shows that the system clock frequency is 578MHz and the throughput is about 520 Msymbols/s.Comparing with the published works by the same technology library at home and abroad,they are optimized by 40% and 26% at least respectively.%研究了JPEG2000算术编码器的算法和电路实现.提出了重归一化规程的一种新的顺序结构,通过添加独立的总移位次数预测规程,使得编码算法可以一次性顺序完成当前上下文的处理.据此设计了具有从流水线的三级流水线电路结构,流水线用于处理无编码字节输出的常规情况,从流水线单独处理编码字节的输出,从而有效缩短了各级电路的关键路径延时.基于TSMC 0.18μm工艺的综合结果表明,系统时钟频率为578MHz,吞吐量约为520Msymbols/s.与采用相同工艺的国内外研究成果相比,分别提升了40％和26％以上.