A kind of method is consistently arranged to design and verify a kind of system for designing a JPEG (joint photographic experts group) 2000 encoder, by being designed according to a hardware configuration modeling algorithm and reaching the design water level being combined into using same test vector. One JPEG2000 encoders are modeled in a UTF (without synchronous function) levels (S210), and the processing time of each module is compared (S220). One DWT (wavelet transform) module and one layer of -1 module are separated the long processing time to implement module, with hardware (S230). One control signal and a data-signal are a master/slave library modelings by using SystemC (S240). Time information increases the redesign executed in BCA (accurate bus cycles) level, and wherein it is synchronous with a table clock (S250) to carry out operation for system operatio. By using DWT modules (S260), design is combined with heterogeneous IP (agreement of intelligence), is shown. One MQ (multiple digital converter) encoder is generated in -1 module of layer to improve the relationship between a software module and a hardware module (S270).
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