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机译:隧道FET架构的器件和电路级性能比较以及异构栅极电介质的影响
Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi-110021, India;
Department of Electronics, Deen Dayal Upadhyaya, College, University of Delhi, New Delhi 110015, India;
Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi 110086, India;
Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi-110021, India;
Ambipolar; hetero gate (HG); p-i-n; p-n-p-n; propagation delay; tunneling field-effect transistor (TFET);
机译:异构栅极电介质对DC,RF和电路液位性能的影响源袋工程GE / Si异质结垂直TFET
机译:研究轻掺杂和异质栅介电碳纳米管隧穿场效应晶体管以改善器件和电路级性能
机译:界面陷阱电荷对异质栅介质电掺杂隧道FET性能的影响
机译:基于TCAD评估的电路级性能比较研究源口袋工程术语All-Si垂直隧道FET和GASB / SI异质结垂直隧道FET
机译:浮栅纳米晶体FET器件和电路的建模和仿真。
机译:单pMOSFET介电性能下降对NAND电路性能的影响
机译:完整siGe的器件改进和电路性能评估 双栅隧道FET
机译:微波半导体研究 - 材料,器件,电路。采用埋地金属栅的Gaas弹道电子晶体管。