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首页> 外文期刊>Journal of multiple-valued logic and soft computing >Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates
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Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates

机译:使用通用三元门的通用子集最小化三元可逆逻辑级联

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摘要

Universal MS gates for multiple-valued quantum circuits have been introduced recently by Muthukrishnan and Stroud, as well as their realization using ion trap devices [11]. No synthesis algorithm was however given neither experimental results of its application. Here we present an algorithm that creates a cascade of gates from the gate family introduced in [11]. The algorithm starts from ternary reversible function specification and always terminates. It does not require ancilla bits. The algorithm can find a solution for any reversible ternary function with n inputs and n outputs utilizing gates such as five single-qubit ternary inverter gates and the subset of two-qubit ternary Generalized Controlled Gates. The algorithm is a generalization of the algorithm presented by Dueck, Maslov, and Miller in [3] to ternary logic and new type of gates. A compaction algorithm is defined to improve the results of the basic algorithm. Three variants of search are compared.
机译:Muthukrishnan和Stroud最近引入了用于多值量子电路的通用MS门,以及使用离子阱设备实现的通用门[11]。但是没有给出综合算法,也没有给出其应用的实验结果。在这里,我们提出一种算法,该算法根据[11]中介绍的门系列创建门级联。该算法从三元可逆函数规范开始,并且始终终止。它不需要辅助位。该算法可利用门(例如五个单量子位三进制反相器门和两个量子位三元通用受控门的子集)找到具有n个输入和n个输出的任何可逆三元函数的解决方案。该算法是Dueck,Maslov和Miller在[3]中提出的针对三进制逻辑和新型门的算法的概括。定义了压缩算法以改善基本算法的结果。比较了三种搜索方式。

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