Low-variability negative and iterative spacer processes for sub-30-nm lines and holes

摘要

Continued complementary metal-oxide semiconductor (CMOS) technology scaling is limited not only by the lithography challenges associated with printing subwavelength features, but also by the heightened sensitivity to variation in these features. In modern, highly scaled transistors, small variations in gate length can result in large threshold voltage (VT) shifts by mechanisms such as VT roll-off or drain-induced barrier lowering (DIBL). Variations in transistor width can result in drive current variations and, in the case of narrow devices, threshold voltage shifts as well. In this manner, critical dimension (CD) variations can significantly alter the drive strength of a transistor, thereby affecting the timing or possibly even the functionality of critical circuits, such as static random access memories (SRAM) cells and ring oscillators. Among the causes of CD variations, line edge roughness (LER) is a major challenge for continued scaling. As the nominal CD scales down, LER remains roughly constant, resulting in proportionally larger variations for narrower CDs.