An RSA Co-processor Architecture Suitable for a User-Parameterized FPGA Implementation

摘要

This paper describes an original and straightforward architecture for a logic circuit implementation of the RSA algorithms. The architecture is ideal for teaching advanced undergraduate or graduate students topics associated with public-key cryptography and digital system design. The system is designed with VHDL for execution on a FPGA. Software implementations of RSA running on standard PCs are relatively slow as standard microprocessors are not optimized for the operations RSA must carry out. A key aspect of this approach is the use of Montgomery Multiplication, a method for performing fast modular multiplication.