CLOCK-PULSE CONTROL MOS CURRENT MODE LOGIC (CPC-MCML): A NEW LOW-POWER HIGH-PERFORMANCE LOGIC STYLE

摘要

This paper presents a new reduced swing logic style called clock-pulse control MOS current mode logic (CPC-MCML) that utilizes the current mode scheme to reduce dynamic power and enhance performance. In the mean time, CPC-MCML circuits utilize the dynamic operation to cancel static power dissipation associated with current mode logic circuits. Therefore, CPC-MCML achieves high performance and low-power dissipation. Simulation results show that CPC-MCML circuits have better performance in terms of power, delay, power delay and energy delay products compared to other logic styles. A 4-bit CPC-MCML ripple adder (RCA) is implemented and compared against CMOS, Domino and MCML. CPC-MCML adder achieves 90% and 50% reduction in power delay product (POP) over CMOS and MCML respectively.