False Error Vulnerability Study of On-line Soft Error Detection Mechanisms

摘要

With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the Double Sampling checker (used in Razor), is the simplest and most area and power efficient, but suffers from very high false detection rates of 1.15 times higher than the actual error rates. We also find that the alternate approaches of Triple Sampling and Integrate & Sample method can be designed to have zero false detection rates, but at an increased area, power and implementation complexity. The Triple Sampling method has about 1.74 times the area and 1.83 times the power as compared to the Double Sampling method and also needs a complex clock generation scheme. The Integrate & Sample method needs about 6% more power and is 0.58 times the area of Double Sampling. It comes with more stringent implementation constraints as it requires detection of small voltage swings. We also analyse for Double Transient Faults (DTFs) and show that all the methods are prone to DTFs, with Integrate & Sample method being more vulnerable.