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首页> 外文期刊>Journal of Electronic Packaging >Wiresweep Reduction via Direct Cavity Injection During Encapsulation of Stacked Chip-Scale Packages
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Wiresweep Reduction via Direct Cavity Injection During Encapsulation of Stacked Chip-Scale Packages

机译:在堆叠的芯片级封装封装过程中通过直接腔注入减少线扫

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As packaging continues to offer challenges with variable stacked die configurations of increasing complexity, traditional transfer mold encapsulation faces challenges in defining a robust process window. A major concern is the problem of "wiresweep," wherein deformation of the wirebond during the mold process can potentially cause shortcircuit-ing. Several prior studies have focused on qualifying the effects of various wirebond and mold process parameters on package wiresweep, but most of these studies are restricted to single (discrete) die packages. This paper attempts to fill this gap of knowledge by experimenting with a variety of test vehicles with different stacking configurations. Specifically, the effects of varying loop height, stack height, and mold compound type are quantified in terms of maximum wiresweep. We find that loop height can have a considerable effect on wiresweep, with the maximum wiresweep being reduced by half (from around 6% to less than 3%) simply by reducing the loop height. Additionally, the study finds that for a given mold process, higher die stacks tend to increase wiresweep, although a threshold stack height exists beyond which further stacking can reduce wire-sweep. Lastly, the data suggest that the choice of mold compound can adversely impact wiresweep, especially for test vehicles with traditionally high wiresweep. Having identified these trends, semianalytical models from the literature are used to investigate the cause behind these observations. The analysis suggests that the mold front velocity has the major root impact on package wiresweep. To validate this hypothesis, the series of tests conducted earlier is repeated for a compression mold process, which provides greater control over the mold front velocity. As predicted by the model, significant reduction in wiresweep is achieved. Thus, the compression mold process seems to offer the opportunity for reducing wiresweep without any compromise in the complexity of the die stack.
机译:随着封装在复杂性不断增加的可变堆叠裸片配置方面继续带来挑战,传统的传递模具封装面临着定义坚固的工艺窗口的挑战。一个主要问题是“线扫”问题,其中在模制过程中引线键合的变形可能潜在地引起短路。先前的一些研究集中在验证各种引线键合和模具工艺参数对封装线扫的影响,但这些研究大多数限于单(离散)管芯封装。本文尝试通过对具有不同堆叠配置的多种测试车辆进行试验来填补这一知识空白。特别是,根据最大线扫量来量化变化的套环高度,叠层高度和模塑料类型的影响。我们发现,回路高度可以对扫线产生相当大的影响,仅通过减小回路高度,最大扫线就可以减少一半(从大约6%到小于3%)。此外,研究发现,对于给定的模具工艺,较高的管芯堆叠会增加线扫,尽管存在阈值堆叠高度,超过该阈值时,进一步的堆叠可以减少线扫。最后,数据表明,模塑料的选择会对线扫产生不利影响,特别是对于传统上使用高线扫的测试车辆而言。在确定了这些趋势之后,使用文献中的半分析模型来调查这些观察结果的原因。分析表明,模具前部速度对封装线扫的影响最大。为了验证该假设,对压缩模具过程重复进行了较早的一系列测试,从而对模具的正面速度提供了更好的控制。正如模型所预测的,线扫明显减少了。因此,压缩模制工艺似乎提供了减少丝线缠绕的机会,而丝毫不影响芯片堆叠的复杂性。

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