A Cap-less Voltage Spike Detection and Correction Circuit for Low Dropout Regulator

摘要

A cap-less voltage spike detection and correction circuit for flipped voltage follower (FVF)-based low dropout regulator (LDO) is proposed in this paper. The transients in the output voltage are controlled by the pull-up currents IUP1 and IUP2 and pull-down currents IDN1 and IDN2. These currents are dynamic current sources which are activated only during transient period and noise contributed by these current sources at steady state is zero. These currents increase/decrease based on the intermediate FVF node voltage VX. The proposed circuit detects the output voltage via VX and controls the power MOSFET gate and output capacitances by changing the pull-up and pull-down currents whenever the load changes. The proposed circuit consumes small additional bias current in the steady state and achieves less settling time and output spike voltage. This LDO is simulated using 180 nm technology and the simulation result shows that the LDO has good load transient response with 190 ns settling time and 170 mV voltage spike over 1 mA to 100 mA load current range.