A Hybrid Countermeasure-Based Fault-Resistant AES Implementation

摘要

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AKS) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid counterineasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the counterineasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed counterineasure is about 14% and the additional time delay is about 13%.