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The double mode AES implementation which supports single unit and multiplex AES operation
The double mode AES implementation which supports single unit and multiplex AES operation
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机译:支持单单元和多路AES操作的双模式AES实现
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摘要
An apparatus comprising a mode circuit and an encryption circuit. The mode circuit may be configured to selectively provide register input data ON an output signal when in a first mode and memory data ON the output signal when in a second mode. The encryption circuit may be configured to interchangeably encrypt/decrypt between the register input data and the memory data.
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