An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure

摘要

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-mu W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and V-DD = 0.9-V supply voltage with the sample rate of 140 MS/s show SFDR > 64.37dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.