A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

摘要

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16 way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track and-hold stage samples the 800-mV(PP) differential input signal at 10 GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8 mW. At a sampling rate of 10 GS/s, -41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5 GHz.