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Non-planar substrate effect on the interface trap capacitance of metal-oxide-semiconductor structures with ultra thin oxides

机译:非平面衬底对具有超薄氧化物的金属氧化物半导体结构的界面陷阱电容的影响

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摘要

Redistribution of interface trap capacitance (Cit) was observed in non-planar substrate metal-oxide-semiconductor (MOS) capacitors with ultra thin oxides. It was found that the behavior of Cit of non-planar substrate MOS capacitors is dependent on the non-planar portion. The non-planar devices exhibit two peaks distribution in Cit due to multiple surfaces effect. A Cit model combining uniform and non-uniform areas effect was proposed for the observation. The non-uniform substrate MOS capacitors exhibit significant non-uniform deep depletion behaviors and degradation in constant voltage stress reliability.
机译:在具有超薄氧化物的非平面衬底金属氧化物半导体(MOS)电容器中观察到界面陷阱电容(Cit)的重新分布。已经发现,非平面基板MOS电容器的Cit行为取决于非平面部分。由于多重表面效应,非平面器件在Cit中显示两个峰分布。提出了结合均匀面积和非均匀面积效应的Cit模型进行观测。不均匀的衬底MOS电容器表现出明显的不均匀的深度耗尽行为和恒定电压应力可靠性的下降。

著录项

  • 来源
    《Journal of Applied Physics》 |2012年第9期|p.1-7|共7页
  • 作者

    Tseng Po-Hao; Hwu Jenn-Gwo;

  • 作者单位

    Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
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