Modeling of high-frequency capacitance-voltage characteristics to quantify trap distributions near SiO_2/SiC interfaces

摘要

A procedure to calculate capacitance-voltage (C-V) characteristics from numerical solutions of the Poisson equation for metal-oxide-semiconductor (MOS) capacitors with traps located both at the oxide/semiconductor interface and in the semiconductor is presented. This method is tested for the simple case of a uniform distribution of a single acceptor or donor level in the semiconductor, for which an approximate analytical solution was derived by analogy with the results obtained for a Schottky diode within the depletion approximation. This method is then applied to model the high-frequency C-V curves of n-type 4H- and 6H-SiC MOS capacitors, which show a kink at depletion bias voltages that broadens with decreasing temperature below 150K. This feature of the high-frequency capacitance occurs at the same temperature and voltage range as a signal detected by constant capacitance deep-level-transient spectroscopy (CCDLTS) measurements and attributed to SiC traps. When only interface traps are considered, the trap energy distribution that is required to reproduce the kink in the C-V curves is not consistent with the trap energy distribution determined from CCDLTS measurements. Numerical simulations show that traps in the SiC epi-layer near the SiO_2/SiC interface as well as interface traps with energies close to the SiC conduction band are necessary to explain both the CCDLTS measurement results and the temperature dependence of C-V curves.