Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor

摘要

A simple and efficient strain engineering technique for integrating the tensile-stress contact etch stop layer (CESL) process to a notch gate has been reported in detail. The strain engineering technique utilizes slight process modifications to modulate the channel stress and implantation profile for the enhancement of performance without adding any extra process steps. Compared with the conventional vertical-gate complementary metal oxide semiconductor field effect transistor (CMOSFET) with an offset spacer, a device with a notch gate as a self-aligned offset spacer achieves an extra 7% NMOS I_(ON) enhancement. The enhancement comes from the larger channel stress induced by the tensile-stress CESL on the notch gate, and is confirmed by technology computer aided design (TCAD) simulation. Moreover, fewer interface defects (D_(it)) and parasitic capacitances were obtained for the notch-gate samples.