Layout-Independent Transistor with Stress-Controlled and Highly Manufacturable Shallow Trench Isolation Process

摘要

In this paper, in order to obtain layout-independent transistors in recent fine-pitched LSI circuits, a completely stress-controlled shallow trench isolation (STI) process is proposed. In this process, a single-layered spin-on dielectric (SOD) film is used for STI gap filling without employing a complex hybrid structure. With this technique, the mechanical stress caused by STI is markedly suppressed. Subsequently, drain current (I_d) modulation due to the STI stress is inhibited successfully. Thus, this technique is a very promising 45 nm node STI scheme with a high performance and a high reliability.