首页> 外国专利> METHOD OF FORMING SHALLOW TRENCH ISOLATION IN THE SEMICONDUCTOR MANUFACTURING PROCESS AND SEMICONDUCTOR DEVICE INCLUDING THE SHALLOW TRENCH ISOLATION

METHOD OF FORMING SHALLOW TRENCH ISOLATION IN THE SEMICONDUCTOR MANUFACTURING PROCESS AND SEMICONDUCTOR DEVICE INCLUDING THE SHALLOW TRENCH ISOLATION

机译:在半导体制造过程和半导体装置中形成浅沟槽隔离的方法,包括浅沟槽隔离

摘要

A method for forming a shallow trench isolation and a semiconductor device having the shallow trench isolation are provided to prevent a defect of bullet hole by rounding corners of a bottom portion of the shallow trench isolation through a dry etching and wet etching. An etching mask is formed to expose first and second regions on a substrate(10). The substrate is dry etched by using the etching mask to form a first trench region(40), in which the first and second regions are removed. The substrate between the first and the second regions are wet etched to form a second trench region(70). An insulation layer is formed in the second trench. The etching mask consists of a pad oxide layer(20) and a nitride layer(30).
机译:提供一种形成浅沟槽隔离物的方法和具有该浅沟槽隔离物的半导体器件,以通过干法蚀刻和湿法蚀刻使浅沟槽隔离物的底部的角变圆,从而防止弹孔的缺陷。形成蚀刻掩模以暴露衬底(10)上的第一和第二区域。通过使用蚀刻掩模对基板进行干法蚀刻以形成第一沟槽区域(40),其中去除了第一和第二区域。对第一区域和第二区域之间的基板进行湿法蚀刻以形成第二沟槽区域(70)。在第二沟槽中形成绝缘层。蚀刻掩模由垫氧化物层(20)和氮化物层(30)组成。

著录项

  • 公开/公告号KR100725350B1

    专利类型

  • 公开/公告日2007-05-29

    原文格式PDF

  • 申请/专利权人 DONGBU ELECTRONICS CO. LTD.;

    申请/专利号KR20050132012

  • 发明设计人 KIM BYUNG HO;

    申请日2005-12-28

  • 分类号H01L21/762;

  • 国家 KR

  • 入库时间 2022-08-21 20:32:03

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