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首页> 外文期刊>Japanese journal of applied physics >Reset Current Reduction with Excellent Filament Controllability by Using Area Minimized and Field Enhanced Unipolar Resistive Random Access Memory Structure
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Reset Current Reduction with Excellent Filament Controllability by Using Area Minimized and Field Enhanced Unipolar Resistive Random Access Memory Structure

机译:通过使用面积最小和场增强的单极电阻随机存取存储器结构,以优异的灯丝可控性降低复位电流

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摘要

We firstly propose a novel resistive random access memory (RRAM) cell structure, which makes it possible to minimize the switching area and to maximize the electrical field where resistive switching occurs, resulting in the improvement of resistive switching characteristics. With excellent structural advantages, resistive switching characteristics such as reset current and set voltage fluctuation are improved through the enhancement of conductive filament (CF) controllability. A simple fabrication process is delivered and the device performance from the viewpoints of the forming voltage, set voltage, and reset current is investigated. Conducting defect effects are also investigated in comparison with the conventional RRAM cell structure. Numerical simulation is performed using a random circuit breaker (RCB) model to confirm the proposed structure.
机译:首先,我们提出了一种新颖的电阻式随机存取存储器(RRAM)单元结构,该结构使得可以最小化开关面积并最大化发生电阻开关的电场,从而改善了电阻开关特性。凭借出色的结构优势,通过增强导电丝(CF)的可控制性,改善了电阻开关特性,例如复位电流和设定电压波动。提供了一种简单的制造工艺,并从成型电压,设置电压和复位电流的角度研究了器件性能。与常规RRAM单元结构相比,还研究了导电缺陷效应。使用随机断路器(RCB)模型进行数值模拟,以确认提出的结构。

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  • 来源
    《Japanese journal of applied physics》 |2012年第4issue2期|p.04DD07.1-04DD07.6|共6页
  • 作者单位

    Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea,DRAM Process Architecture Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd., Yongin, Gyeonggi 445-701, Republic of Korea;

    Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea,DRAM Process Architecture Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd., Yongin, Gyeonggi 445-701, Republic of Korea;

    Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea;

    DRAM Process Architecture Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd., Yongin, Gyeonggi 445-701, Republic of Korea;

    Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea;

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