On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO_2 for energy efficient sub-0.2 V operation

摘要

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I-on/I-off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I-on/I-off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L-g), FE:HfO2-based DGNCFET still has a design point for high I-on/I-off ratio. With an optimized gate stack thickness for sub-10 nm L-g, FE:HfO2-based DGNCFET has 2.5x higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V. (c) 2018 The Japan Society of Applied Physics