On gate stack scalability of Double-Gate Negative-Capacitance FET with ferroelectric HfO2 for energy-efficient sub-0.2V operation

摘要

We have investigated a Double-Gate Negative Capacitance FET (DGNCFET) with CMOS-compatible ferroelectric HfO2 (FE:HfO2) gate insulator and demonstrated high Ion/Ioff and Steep Subthreshold Swing (SS) for sub-0.2V operation by analytical model and simulation. Gate insulator and interfacial layer thickness dependence has been systematically studied for FE:HfO2 under process technology constraint, for the first time. The optimum gate stack can fit to the aggressively scaled Lg and it enables 2× higher energy efficiency at <;0.2V than conventional DGMOSFET.