A CMOS Cell Layout Generation System for Two-dimensional Thansistor Placement

摘要

This paper presents an automatic layout generation system for CMOS uniform height cells with a two-dimensional transistor placement. The two-dimensional transistor placement attains dense layouts for such cells as consist of considerably varied sizes of transistors. Transistors are arranged automatically in the two-dimensional layout style using a branch-and-bound method, and a maze router is used to complete the required connections while minimizing the cell layout width. To demonstrate the effectiveness of the proposed two-dimensional layout method, we compared cell layouts generated by the proposed system with those in the traditional one-dimensional layout style, for various cell heights. As a result, we conclude that two-dimensional layout style is effective in terms of the resulting cell layout agret for cells which consist of various sizes of transistors. Moreover, the experimental results show that the generated layouts are comparable in terms of cell layout area to manual layouts done by skilled layout designers.