Minimized Memory Architecture for Low Latency Viterbi Decoder using Zig-zag Algorithm

摘要

This paper proposes a new architecture for efficient and minimized memory management in Viterbi Decoders based on Zig-Zag algorithm. The memory organization techniques mainly deal with the storage of survivor sequences from which the decoded information sequence is retrieved. The survivor sequences are usually stored in RAM blocks and traced back. Register Exchange (RE) Method and Trace-Back (TB) Method have been used for memory management techniques. Due to large memory area utilization of these two methods, a new architecture is implemented in this paper. This method uses only a single RAM instead of two (used in Trace-Back Method), which performs storage as well as trace-back simultaneously. The implementation shows that the memory size has been reduced to 56.09% when compared to the trace-back (TB) Method. The trade off in latency has been compensated by optimization of the parameters and it has been reduced to 50%. The architecture based on Viterbi Decoder has been implemented with a constraint length of 4, code rate of 1/6 and the traceback depth of 20.