Algorithms and architectures for high-speed Viterbi decoding.

摘要

In recent years there has been interest in the implementation of the Viterbi algorithm at rates of 100Mb/s and higher. Driving applications include convolutional decoders for error correction, trellis code demodulation for communication channels, and digital sequence detection for magnetic storage channels.;A unified matrix-based approach is proposed for the state metric update of trellises based on shift register processes. This unified framework provides a systematic procedure for architecture synthesis and is used to derive a number of new higher throughput cascade Viterbi decoder architectures. Trading higher clock rates for reduced complexity, these architectures provide more area-efficient solutions to many decoding problems currently implemented using fully parallel architectures.;A new approach to survivor path decode is proposed based on hybrid architectures that combine the register-exchange and trace-back methods, yielding overall area reductions while maintaining throughput. Two hybrid architectures are proposed: hybrid pretrace-back and hybrid trace-forward. Both of these architectures can be implemented using a single compact decision memory and are up to 40% smaller in area than conventional trace-back architectures.;The classical high throughput decoder for a binary shift register process is the radix-2 fully parallel architecture. The throughput of this approach is fundamentally limited by either the recursive add-compare-select (ACS) iteration or the recursive trace-back iteration. An alternative architecture is proposed based on a radix-4 ACS iteration and a radix-16 trace-back iteration that offers a potential two-fold increase in throughput. The radix-4/radix-16 architecture is demonstrated in a R = 1/2, 32-state decoder implemented using 1.2;To achieve unlimited concurrency and hence throughput without constraining the encoding process, a sliding block Viterbi decoder (SBVD) is proposed that combines the filtering characteristic of a sliding block decoder with the computational efficiency of the Viterbi algorithm. For systolic implementation the SBVD method is superior to the recently proposed minimized method in terms of decoder performance and complexity. The systolic SBVD architecture is demonstrated in a R = 1/2, 4-state decoder implemented using 1.2