A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS

摘要

The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging. Hence, to reduce the turnaround time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable Pacube (PA~3 — Programmable Array of Array Adders) VLSI array is proposed in this paper. These arrays can be mask programmed for building cost-effective super computing VLSI functional units. Another important feature is the architecture of the macro-cell, which is designed in such a way that the functional units corresponding to the G-set equations when mapped on the macro-cell arrays possess identical data flow control. This leads to a highly simplified control design for executing complex computations.