A METHOD FOR PERFORMANCE MODELING AND EVALUATION OF LDPC DECODER ARCHITECTURE

摘要

This paper presents a high-throughput memory efficient decoder for low density parity check (LDPC) codes in the high-rate wireless personal area network application. The novel techniques which can apply to our selected LDPC code is proposed, including parallel blocked layered decoding architecture and simplification of the Wigig networks. State-of-the-art flexible LDPC decoders cannot simultaneously achieve the high throughput mandated by these standards and the low power needed for mobile applications. This work develops a flexible, fully pipelined architecture for the IEEE 802.11ad standard capable of achieving both goals. We use Real Time-Performance Evaluation Process Algebra (RT-PEPA) to evaluate a typical LDPC Decoder system's performance. The approach is more convenient, flexible, and lower cost than the former simulation method which needs to develop special hardware and software tools. Moreover, we can easily analyze how changes in performance depend on changes in a particular mode by supplying ranges for parameter values.