Implementation of Low Power Digital Circuits using DFAL Technique

摘要

Power Dissipation being an important parameter of any electronic system's performance is a major topic of interest for scads of researchers. Frequency divider, a basicbuilding block in ample electronic systems, dissipates a very high power and consumes substantial amount of energy. In this papera frequency divider-by-3 circuit is implemented using diode freeadiabatic logic (DFAL), which surpasses the static CMOS logicbased inverter and frequency divider-by-3 in terms of power dissipation and power delay product (PDP). The functionality of the implemented circuit is verified through TSPICE simulations inTanner EDA simulator by using 0.25 micron technologyparameters. For the performance measures, average powerdissipation and PDP of the DFAL based frequency divider-by-3 circuit iscompared with its static CMOS counterpart. The simulation results constant input frequency analysis confirm the superiority of DFAL based frequency divider-by-3.