机译:QCA的模块化设计带有流量加法器和乘法器,减少了导线交叉和逻辑门的数量
Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China;
Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China;
Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China;
Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China;
Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China;
Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China;
quantum-dot cellular automata; modular design; Tile CFA; Tile CDM; DC Tile CDM; QCADesigner;
机译:利用可逆逻辑门设计最优的随身跳动加法器和随身跳动BCD加法器
机译:可逆逻辑门设计最优的随身跳动加法器和随身跳动BCD加法器科学出版物
机译:采用CMOS技术的紧凑型随身加法器,半加法器和全加法器的低功耗减薄壁乘法器的设计
机译:针对QCA逻辑电路中最小导线交叉的通用逻辑门设计
机译:高速加法器和阵列乘法器的动态电流模式逻辑电路的分析和设计。
机译:一种使用QCA实现具有成本效益的算术逻辑电路的新型可逆逻辑门及其系统方法
机译:使用可逆逻辑门设计最佳进位跳过加法器和进位跳过BCD加法器