An 11-W, 9-bit fully differential, cyclic/algorithmic ADC in 0.13m CMOS

摘要

This paper describes a fully differential, cyclic, analogue-to-digital converter (ADC). It utilizes a 4-bit binary weighted capacitor array to obtain 9-bit resolution. The ADC uses an operational amplifier to suppress supply voltage variations. The operational amplifier with the slew-rate detection is used to increase the speed of the ADC. The ADC is fabricated in IBM 0.13m CMOS process and occupies 650x850m(2) active area. At 10kS/s sampling rate, the ADC consumes 11W. In order to test immunity of the ADC on the supply voltage variations, static and dynamic performance of the ADC is measured with triangular supply voltage (V-DC=1.5V, V-AC=200mV(pp), f=1kHz). The measured peak of differential nonlinearity and integral nonlinearity is +0.26/-0.67 and +0.65/-0.59, respectively. At 250Hz, effective number of bit is 8.4bits, SFDR=66.7dB and SNDR=52.6dB. Copyright (c) 2016 John Wiley & Sons, Ltd.