Automation of clock distribution network design for digital integrated circuits using divide and conquer technique

摘要

One of the most carefully engineered components of a digital integrated circuit is the clock distribution network. A clock is unarguably the most important signal and the network used for its distribution contributes to nearly half of the entire power dissipated by the IC. The design of a clock distribution network requires tremendous resources in terms of time and effort to achieve optimized results. This paper discusses the development of a new algorithm with smaller time complexity for automation of the design of clock distribution network that can greatly reduce the time and effort required, at the same time meeting the conditions set for delays and maximum allowable power dissipation.