An on-chip frequency programmable test clock generation and application method for small delay defect detection

摘要

Small delay defects are posing a serious challenge to the quality and reliability of modern fabricated chips. A promising way for screening the timing-related defects in nanometer technology designs is faster-than-at-speed delay testing. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip frequency-programmable test clock generation method which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. With a reconfigurable launch-and-capture clock generator (LCCG) embedded on-chip, the required test clock, with a reconfigurable frequency and a high resolution, can be achieved by specifying the control information in the test patterns, which is then used to configure the LCCG. Similarly, the control information regarding test framework and clock signal selection can also be embedded in the test patterns. Experimental results are presented to validate the proposed method. (C) 2014 Elsevier B.V. All rights reserved.