Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System

摘要

Current-mode signalling scheme is one of the prominent solutions for high-speed and high data rate communication in global on-chip interconnects. Advancements in nanofabrication processes and housing of billions of transistors on a single silicon chip have made process-induced variations in transistors and interconnects quite significant. Analysis of parameter variations has become an important step in predicting the reliability and addressing various electronic circuit design issues in nanoscale regimes. The present paper evaluates the stochastic parameters variability on the electrical performance of on-chip current-mode interconnect system. Both transistor and interconnect variability effects are analyzed. Interconnect is modelled by an equivalent distributed line model and is driven by a current-mode driver. The impact of variability is assessed via parametric, process corner and Monte-Carlo analyses. The variability analysis is carried out for single as well as coupled 2-Line, 3-Line and 5-Line interconnect structures. Furthermore, the impact of individual process parameter variability in current-mode interconnect system has been investigated using statistical techniques namely Taguchi design of simulation scheme, ANOVA and Rank table.