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A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells

机译:用于细胞合成的二维晶体管放置算法及其在标准细胞中的应用

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摘要

We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.
机译:我们提出了一种晶体管放置算法,以二维放置样式生成标准单元布局。该算法在第一阶段优化一维放置,在第二阶段折叠大晶体管,并在最后阶段优化二维放置。我们还根据布线长度提出了“成本函数”,它与单元优化紧密匹配。此晶体管放置算法已应用于多个标准单元,并展示了生成与手动设计放置相当的二维放置的功能。

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