TCAD Driven Drain Engineering for Hot Carrier Reduction of 3.3 V I/O PMOSFET

摘要

In this paper, we propose a TCAD driven hot carrier reduction methodology of 3.3 V I/O pMOSFETs design. The hot carrier reliability of surface channel I/O pMOSFET having drain structure in common with core devices has a critical issue. It is substantially important for the high-reliability devices to reduce both drain avalanche and channel hot hole components. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and drive current (I_(ON)). SDE/HALO of both core and I/O transistors can be totally optimized for reduction of process-steps and/or photo-masks.