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首页> 外文期刊>IEICE Transactions on Electronics >Voltage-Mode Multiple-Valued Logic Adder Circuits
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Voltage-Mode Multiple-Valued Logic Adder Circuits

机译:电压模式多值逻辑加法器电路

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摘要

Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.
机译:介绍了多值逻辑(四进制)半加法器,全加法器和超前进位加法器的新颖设计。所提出的电路是静态的,并且在电压模式下工作。而且,在稳定状态下没有电流流动,因此没有静态功耗。尽管在晶体管数量上的比较表明所提出的四进制电路大于两个相应的二进制电路,但使用多值逻辑可带来并行加法的好处。首先,由于进位的数量是二进制进位的一半,并且进位到输出进位的传播延迟相对较小,所以纹波进位加法更快。其次,超前进位方案显示出较少的复杂性,这导致总数量增加的晶体管数量的整体减少。

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