Design and Implementation of the High-Speed IPv6-IPv4 Translator and Analysis of Its Performance

摘要

In this paper, we propose high performance IPv6-IPv4 translator, which translates all packets between IPv6 networks and IPv4 networks at high speed. In our previous work, we analyzed the performance factors of the existing S/W IPv6-IPv4 translators and proposed the improvement methods of each factor. To realize these methods, we also design and implement the IPv6-IPv4 translator with hardware core for the high-speed translation. To verify functionality of our translator core, the hardware emulation using prototyping as well as simulation is performed. Moreover, we show that our translator core can support high-performance translation.