High Current Drivability FD-SOI CMOS with Low Source/Drain Series Resistance

摘要

A high current drivability CMOS on Si(lOO) with a low Source/Drain series resistance is demonstrated using a fully-depleted silicon-on-insulator (FD-SOI) technology. The pMOS current drivability is improved by an introduction of the accumulation-mode device structure. Also, the contact resistivity as well as, the sheet resistance of the Source/Drain (S/D) electrodes are reduced to 6.9 × 10~(-9) Ω·cm~2 for n~+-Si and 8.0 × 10~(-10) Ω·cm~2 for p~+-Si and 5 Ω/sheet due to an introduction of work function optimized silicides for nMOS and pMOS, and a metal/silicide/Si stack structure, respectively. As a result, current drivability of 833 uA/um and 661 μA/μm for nMOS and pMOS are obtained for around 100 nm gate length device size.