ソフトエラー耐性を考慮した論理回路の設計においてソフトエラー耐性評価手法が必要となる．順序回路におけろ評価手法の1つに厳密にソフトエラー発生後の振る舞いを解析する手法が提案されているが、実行時間の観点から問題がある．それに対し，ソフトエラー発生後の1クロックのみを考慮する近似手法も提案されているが，この手法では計算精度の観点から問題がある．そのため本稿では，複数クロックを考慮した近似評価手法について述べ，計算精度および実行時間の評価を行う．%Soft error tolerance estimation method is necessary for soft error aware logic designs. There is an exact method has been proposed to estimate soft error tolerance for sequential circuits. This method can analyze the behavior of state transitions strictly with Markov model. This method has difficulty applying for large scale circuits, because this method needs run time exponential in the size of circuits. On the other hand, there is an approximate method which considers the behavier of circuits for only 1 clock-cycle after soft error occurring. This method has a problem which has low accuracy. This paper presents an approximate methods. The method is more accurate than the existing approximate method, because it considers the behavior of circuits for several clock-cycles.
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