A new architecture for the implementation of high-order decimation filters is described. It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filter's passband response. This allows the first-stage CIC decimation filter to be followed by a fixed-coefficient second-stage filter, rather than a programmable filter, thereby achieving a significant hardware reduction over existing approaches. Furthermore, the use of fixed-coefficient filters in place of programmable-coefficient filters improves the overall throughput rate. The resulting architecture is well suited for single-chip VLSI implementation with very high data-sample rates. We discuss an example with specifications suitable for use in a wideband satellite communication subband tuner system and for signal analysis.
展开▼
