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Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse

机译:快速计算离散傅里叶变换及其逆的高效VLSI架构

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In this paper, we propose two new VLSI architectures for computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT) based on a radix-2 fast algorithm, where N is a power of two. The first part of this work presents a linear systolic array that requires log/sub 2/ N complex multipliers and is able to provide a throughput of one transform sample per clock cycle. Compared with other related systolic designs based on direct computation or a radix-2 fast algorithm, the proposed one has the same throughput performance but involves less hardware complexity. This design is suitable for high-speed real-time applications, but it would not be easily realized in a single chip when N gets large. To balance the chip area and the processing speed, we further present a new reduced-complexity design for the DFT/IDFT computation. The alternative design is a memory-based architecture that consists of one complex multiplier, two complex adders, and some special memory units. The new design has the capability of computing one transform sample every log/sub 2/ N+1 clock cycles on average. In comparison with the first design, the second design reaches a lower throughput with less hardware complexity. As N=512, the chip area required for the memory-based design is about 5742/spl times/5222 /spl mu/m/sup 2/, and the corresponding throughput can attain a rate as high as 4M transform samples per second under 0.6 /spl mu/m CMOS technology. Such area-time performance makes this design very competitive for use in long-length DFT applications, such as asymmetric digital subscriber lines (ADSL) and orthogonal frequency-division multiplexing (OFDM) systems.
机译:在本文中,我们提出了两种新的VLSI架构,用于基于radix-2快速算法来计算N点离散傅里叶变换(DFT)及其逆(IDFT),其中N是2的幂。这项工作的第一部分介绍了一个线性脉动阵列,该阵列需要log / sub 2 / N个复数乘法器,并且能够提供每个时钟周期一个变换样本的吞吐量。与其他基于直接计算或基数为2的快速算法的相关收缩设计相比,所提出的收缩性能相同,但硬件复杂度较低。该设计适合于高速实时应用,但是当N变大时,很难在单个芯片中实现。为了平衡芯片面积和处理速度,我们进一步提出了一种用于DFT / IDFT计算的新的降低复杂度的设计。另一种设计是基于内存的体系结构,它由一个复数乘法器,两个复数加法器和一些特殊的存储单元组成。新设计具有平均每个log / sub 2 / N + 1个时钟周期计算一个变换样本的能力。与第一种设计相比,第二种设计具有较低的吞吐量和更少的硬件复杂性。当N = 512时,基于内存的设计所需的芯片面积约为5742 / spl乘以/ 5222 / spl mu / m / sup 2 /,并且相应的吞吐量可以达到每秒4M转换样本的速率,低于0.6 / spl mu / m CMOS技术。这种时空性能使该设计在诸如非对称数字用户线(ADSL)和正交频分复用(OFDM)系统等长DFT应用中具有很高的竞争力。

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