Reduced Complexity Soft-Output MIMO Sphere Detectors—Part II: Architectural Optimizations

摘要

In Part I, we presented algorithmic optimizations for a soft-output (SO) tree-search MIMO detector targeted at reducing the node count complexity for a given error-rate performance. We present in this part the architecture for a hardware-efficient pipelined detector that incorporates all these optimizations. A detailed gate complexity analysis of the architecture is conducted, including arithmetic optimizations to minimize the use of multipliers for distance computations by exploiting the lattice structure, as well as efficient pointer logic for implementing child enumeration, internal node-pruning and node-skipping steps. For multitone OFDM symbol detection using multiple tree-search detectors, we propose an efficient scheduling scheme that exploits the slack in node count from tone-to-tone detection. By ordering the tones according to increasing order of their channel matrix orthogonality defect, the detector maximizes the slack of early terminating detectors and forwards it to ill-conditioned tones that require more detection time. Case studies and simulation experiments were conducted based on a 4-layer 64-QAM MIMO system for LTE. Simulations and VLSI synthesis results demonstrate that the proposed optimizations require a chip area of only 85 kGE to implement a 64-QAM SO MIMO detector for LTE capable of attaining almost ML performance with an SNR loss of only 0.85 dB.