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Contact Chains for FinFET Technology Characterization

机译:FinFET技术表征的接触链

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摘要

Electrical characterization remains a key element in technology development and manufacturing of integrated circuits. Contact chain is a well known part of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3-D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes a new type of test structure, so-called gated contact chains, developed for contact process characterization in FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g., bad transistor with very high threshold voltage) a series of measurement under various test conditions was performed and analysed. In order to overcome a limitation of the contact chain size and enable data collection from larger sample of contacts, we proposed to implement the gated chains in addressable arrays, increasing their density and failure rate observability. Finally, the paper presents the examples of electrical failure modes detected by those chains in FinFET process.
机译:电气特性表征仍然是集成电路技术开发和制造中的关键要素。接触链是在许多代硅工艺中使用的测试结构诊断集的一个众所周知的部分。在具有3D器件(例如FinFET)的新技术中,这种测试结构的实现变得充满挑战。与此类器件的有源区的接触本质上取决于外延凸起的源极和漏极的体系结构,并且为了进行适当的表征,需要存在晶体管栅极,这为接触设置了环境。本文介绍了一种新型的测试结构,即所谓的门控接触链,它是为FinFET技术中的接触过程表征而开发的。代替简单的接触链,每个结构都包含一系列有源器件,这些有源器件具有用于打开晶体管链以测量链电阻的公共栅电极。为了区分由断开接触或由其他机制(例如,具有非常高的阈值电压的不良晶体管)引起的链故障,在各种测试条件下进行了一系列测量并进行了分析。为了克服接触链大小的限制并允许从较大的接触点样本中收集数据,我们建议在可寻址阵列中实现门控链,从而提高其密度和故障率可观察性。最后,本文介绍了由FinFET工艺中的那些链检测到的电气故障模式的示例。

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