首页> 外国专利> ELECTRICALLY ISOLATED GATE CONTACT IN FINFET TECHNOLOGY FOR CAMOUFLAGING INTEGRATED CIRCUITS FROM REVERSE ENGINEERING

ELECTRICALLY ISOLATED GATE CONTACT IN FINFET TECHNOLOGY FOR CAMOUFLAGING INTEGRATED CIRCUITS FROM REVERSE ENGINEERING

机译:FinFET技术的电隔离栅极接触,用于颠覆逆向工程的集成电路

摘要

A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.
机译:一种用于添加源触点,漏极接触和表观栅极接触的系统和方法到具有包括源区,漏区的翅片的鳍片和设置在翅片上的栅极上形成一个或多个晶体管结的栅极 。 该方法包括产生向下延伸到电耦合到源区的第一区域的源接触开口,漏极接触开口向下延伸到电耦合到漏极区域的第二区域,以及电动向下向下延伸到第三区域的栅极接触开口 从栅极隔离,并用导电金属填充源接触开口,漏极接触开口和栅极接触开口。

著录项

  • 公开/公告号US2021249363A1

    专利类型

  • 公开/公告日2021-08-12

    原文格式PDF

  • 申请/专利权人 RAMBUS INC.;

    申请/专利号US202117157567

  • 申请日2021-01-25

  • 分类号H01L23;H01L29/66;H01L29/423;H01L29/417;

  • 国家 US

  • 入库时间 2022-08-24 20:33:47

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