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首页> 外文期刊>IEEE Transactions on Semiconductor Manufacturing >Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs
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Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs

机译:异常硅 - 锗(SiGe)在FinFET中外延生长

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摘要

In an advanced complementary metal-oxide-semiconductor (CMOS) technology node, small nano-scopic defects tend to have a significant impact on the yield and reliability of the final product. As the technology advances in fin field-effect-transistors (FinFETs), it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. The process of selective epitaxial growth of silicon-germanium (SiGe) on source/drain (S/D) regions is especially prone to defects due to the complexity of the process, thus giving a very narrow processing window to achieve the desired device, yield and reliability results. In this paper we evaluate a critical defect of "Abnormal epi" seen during the selective epitaxial growth of in-situ boron (B) doped SiGe on FinFETs. Abnormal epi here refers to abnormally large and spurious epitaxial growth defect occurring as random instances on a wafer die. These defects, depending on where in the layout they occur, can lead to catastrophic failure under higher test voltages due to the physical shorting of n and p FET devices. We also explore the process parameters which influence this defect including incoming surface conditions and propose mechanisms that lead to the defect. Further, an optimization of the processing parameters in the integration scheme to minimize the occurrence of these defects leads to yield gain and cost savings required for high volume manufacturing.
机译:在先进的互补金属氧化物半导体(CMOS)技术节点中,小纳米缺陷倾向于对最终产品的产量和可靠性产生显着影响。随着鳍片场效应晶体管(FinFET)的技术进步,控制缺陷程度越来越具有挑战性,同时确保所需的处理参数到位。由于该方法的复杂性,源/漏极(SiGe)在源/漏极(SiGe)的选择性外延生长的过程特别容易缺血,从而提供非常窄的加工窗口,以实现所需的装置,产量和可靠性结果。在本文中,我们评估在掺杂FinFET上的原位硼(B)掺杂SiGe的选择性外延生长期间看到的“异常EPI”的关键缺陷。这里的异常EPI是指在晶片模具上作为随机实例发生异常大的和杂散的外延生长缺陷。根据它们发生的布局的位置,这些缺陷可能导致由于N和P FET器件的物理短路而导致较高的测试电压下的灾难性故障。我们还探讨了影响该缺陷的过程参数,包括传入的表面条件,并提出导致缺陷的机制。此外,整合方案中的处理参数的优化以最小化这些缺陷的发生导致高卷制造所需的增益和成本节约。

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