Fabrication and Characterization of a Low Parasitic Capacitance and Low-Stress Si Interposer for 2.5-D Integration

摘要

This paper presents the fabrication and characterization of a low parasitic capacitance and low-stress Si interposer for 2.5-D/3-D integration of stress sensitive MEMS devices. The glass reflow process is utilized to isolate Si posts (through silicon interposer) from Si substrate of a low resistivity to form vertical electrical interconnection. A process is developed and a dummy Si interposer is fabricated. Using the fabricated samples, the Si interposer is characterized in terms of resistance, parasitic capacitance, breakdown voltage, and residue stress test. Air-gapped Si interconnection is measured with a resistance of 0.9 Ω, a parasitic capacitance of 85.12 fF and a breakdown voltage of 250 V at least. The residual stress of Si interposer is also investigated through infrared flare technology and shows a result that less than 30 MPa around the Si interconnection at 350 °C.